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 Spring 2011 CS302 3 |
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Question No. 1 [Marks: 7] Determine Q output waveform for a negative edge triggered J-K flip-flop with preset, clear and J, K inputs. You are required to draw Q output waveform on timing diagram. Question No. 2 [Marks: 1+2] Provide to-the-point answers to the following questions:
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 2011-06-03 11:31:09  181 KB  1 |
| CS302 Assignment 1 Solution |
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Digital Logic Design (CS302) Assignment Solution # 1. |
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| 2011-04-16 11:47:41 28.5 KB 22 |
 Fall 2010_CS302_5_SOL |
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Assignment
A 4-bit bidirectional shift register is shown in the figure below.
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| 2011-04-02 11:40:22 251.08 KB 4 |
| Fall 2010_CS302_4_SOL |
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Question_1: [marks: 16]
Design a 4-bit asynchronous down counter with truncated sequence that counts down a truncated sequence from 1111 to 0101. On reaching the count value 0100, the counter must preset to 1111.
Also draw its timing diagram.
Question_2: [marks: 2+2]
Provide answers to the following .... |
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| 2011-04-02 11:39:28 105.74 KB 4 |
| Fall 2010_CS302_3_SOL |
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Question_1: [marks: 14]
The following serial data are applied to the flip-flop through the AND gates as indicated in figure below. Determine the resulting serial data that appear on the Q output. There is one clock pulse for each bit time. Assume that Q is initially 0 and that and are HIGH.
Rightmost bits are applied first.
Question_2: [marks: .... |
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| 2011-04-02 11:38:38 78.83 KB 4 |
| Fall 2010_CS302_2_SOL |
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Question_1: [Marks: 10]
Use Karnaugh map to simplify the following SOP expression.
Question_2: [Marks: 10] .... |
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| 2011-04-02 11:37:29 37.52 KB 3 |
| Fall 2010_CS302_1_SOL |
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Question_1: [marks: 6]
Convert following decimal values to binary:
3.25
20.20
Question_2: [marks: 6]
Express each decimal number as an 8-bit number in the 2's complement form:
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| 2011-04-02 11:36:26 22.84 KB 0 |
| Spring 2010 CS302 All Assingments with Solutions |
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This document contains assginments and solutions provided by virtual unversity to the student of CS302 Digital Logic Design during spring 2010 semester. |
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| 2010-10-31 14:47:44 7.82 MB 12 |
| CS302- Digital Logic Design |
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1. F(A,B,C,D) = ∑ (3,7,11,13,14,15) |
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| 2010-09-08 11:44:17 30.5 KB 6 |
| CS302 fall 2009 |
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(a)Determine the decimal value of the signed binary number ‘11101000’ expressed in 1’s complement |
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| 2010-09-08 11:35:44 41.5 KB 2 |
 Solution_Spring 2010_CS302_2 |
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Solution_Spring 2010_CS302_2 |
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| 2010-08-10 11:25:36 179.95 KB 5 |
| Fall 2009_CS302_5_Solution |
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Design and implement D-flip flop based sequential UP/DOWN counter. Which counts from 0 to 7 in UP mode and from 7 to 0 in DOWN mode? You have to give all steps for designing this counter. |
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| 2010-08-10 11:00:41 178.5 KB 2 |
| Fall 2009_CS302_2_Solution |
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Fall 2009_CS302_2_Solution |
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| 2010-08-10 10:59:11 30.5 KB 3 |
| Glossary(CS302 - Digital Logic Design) |
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weight : The value of digit in a number based on its position in the number. |
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| 2010-08-02 15:05:42 149.53 KB 15 |
| FAQs(CS302 - Digital Logic Design) |
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Question: For BCD numbers that add up to an invalid BCD number or generate a carry the number 6 (0110) is added to the invalid number, why ? |
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| 2010-08-02 14:02:48 160.9 KB 12 |